Recorder backup virtual bench
Executed component-corner, charging/balancing, transfer and orderly-shutdown models. The results identify an operating envelope and retain undersized cases as failures of the design condition.
Methods and declared inputs
The 64 cases vary bank capacitance 5.76/10 F, ESR 0.12/0.36 ohm, initial voltage 21.6/24 V, converter efficiency 0.82/0.90, steady load 6/7.2 W and UVLO 10.5/11.5 V. Every case retains the 12 W, 2 s start load and 2 A input current limit.
Charging uses ten capacitors in series, one 80 F and nine 120 F, 0.5 A ideal constant current and a 24 V bank endpoint. At 2.65 V an ideal shunt diverts up to its current capability. The sufficient case needs 1.325 W peak dissipation in one shunt; that is a calculation, not a chosen-part thermal rating.
Leakage balance is a separate steady-state calculation with one cell leaking 40 microamp and nine leaking 100 microamp. Equal parallel resistors are evaluated using V_i = R_i (I_series - I_leak_i) and sum V_i = 24 V. Initial charging imbalance and steady leakage are different constraints.
Selected numerical design: minimum 5.76 F, maximum 0.36 ohm, at least 21.6 V initial bank charge, at least 82% efficiency, UVLO no higher than 10.5 V and 2 A input capability. Load is limited to 12 W for 2 s then 6 W; transfer is limited to 2 ms with the declared output capacitor. The ideal charge model uses a 2.65 V shunt clamp with at least 0.6 A capability for 0.5 A charge. These bounds meet duration, transfer and cell-voltage criteria in the executed models.
The recorder timing model generates one record per second for 120 s and acknowledges a single checkpoint after an assumed 5 s flush. If supply ends first, records remain explicitly unacknowledged. No physical filesystem persistence or recording device was measured.
Executed cases
| study | result |
|---|---|
| 64 component corners | 57 meet 125 s; 7 do not |
| Combined-corner steady-load boundary | 6.4329 W at 125 s |
| 24 V, 3760 uF, 50 milliohm transfer boundary | 16.9379 ms to 21.6 V |
| Ideal active balance charge | 569.34 s; max cell 2.6500 V |
| Worst unbalanced cell | 3.4286 V |
Acceptance checks
| id | description | expected | observed | passed | method |
|---|---|---|---|---|---|
| corner-count | Declared binary component sweep completed | 64 | 64 | True | Full factorial 2^6 sweep |
| corner-energy | All discharge cases conserve energy | Residual < 1e-5 J | 1.0876999567699386e-07 | True | Independent accumulated load/converter/ESR energy vs capacitor energy |
| reference-runtime | Original derated reference meets duration | Runtime >= 125 s | 134.0922539022932 | True | Use existing nonlinear converter/ESR model |
| adverse-runtime | High-load/UVLO corners expose insufficient margin | At least one duration below 125 s | 7 | True | Reject adverse design corners, do not alter the target |
| load-envelope | Maximum steady load is bracketed by known cases | 6 < permissible W < 7.2 | 6.432906285450484 | True | Solve modeled runtime = 125 s at declared combined corner |
| transfer-envelope | Transfer gap has a finite voltage boundary | 2 ms passes and 20 ms fails | 16.937890241897048 | True | Solve nonlinear output capacitor voltage = 21.6 V |
| imbalance | Bank voltage alone allows cell overvoltage | Max cell > 2.7 V | 3.4285714285714293 | True | Independent series-charge formula Q/C for one 80 F and nine 120 F cells |
| clamp | Sufficient ideal balancing current clamps every cell | Max cell <= 2.65 V | 2.65 | True | Piecewise constant-current charging with ideal shunts |
| undersized-shunt | Inadequate shunt remains an adverse case | Max cell > 2.7 V | 3.3608875000015153 | True | Shunt limit 0.05 A against 0.5 A charge |
| charge-refinement | Charge end time converges | Difference <= 0.02 s | 1.4495071809506044e-10 | True | Compare 20 and 10 ms integration steps |
| passive-balance | Leakage sensitivity identifies resistor tradeoff | 27 kohm exceeds 2.7 V; 4.7 kohm within | [{'resistor_ohm': 27000.0, 'max_cell_v': 3.8579999999999997, 'min_cell_v': 2.2379999999999995, 'total_dissipation_w': 0.0022208133333333326, 'meets_2_7_v': False}, {'resistor_ohm': 10000.0, 'max_cell_v': 2.94, 'min_cell_v': 2.34, 'total_dissipation_w': 0.005792399999999999, 'meets_2_7_v': False}, {'resistor_ohm': 4700.0, 'max_cell_v': 2.6538, 'min_cell_v': 2.3718, 'total_dissipation_w': 0.01227054714893617, 'meets_2_7_v': True}] | True | Solve common series current with parallel leakage and equal resistors |
| shutdown | Reference model finishes declared 5 s checkpoint | True | True | True | Explicit 120 s record / 5 s checkpoint timing |
| interruption | Insufficient energy leaves unacknowledged records | Checkpoint false and nonzero uncommitted | {'case': 'Injected early loss', 'runtime_s': 80.0, 'records_generated': 80, 'shutdown_started': False, 'checkpoint_acknowledged': False, 'uncommitted_records': 80, 'target_s': 125.0} | True | Synthetic early cutoff; does not infer physical storage behavior |
Scope of the evidence
This is a completed virtual bench using stated assumptions. Converter loop response, cell temperature dependence beyond the declared corners, short-circuit protection and physical recorder durability are outside the reduced model.
No manufacturer part numbers, PCB, wiring release or electrical safety approval are implied. Shunt behavior, leakage and efficiency are analyst inputs; the spreadsheet-like resistor tradeoff is not a product recommendation.
An actual power-path device can fail short or leak. Ideal reverse isolation remains a topology assumption and is not established by the energy model.
Reproduce
python -m pip install -r requirements.txt python run.py
Acceptance matrix · Evidence record and source hashes · Original analysis
Selected numerical design envelope
